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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5461a single phase, bi-direct ional power/energy ic features ? energy data linearity: 0.1% of reading over 1000:1 dynamic range on-chip functions: - instantaneous voltage, current, and power - i rms and v rms , apparent and active (real) power - energy-to-pulse conversion for mechanical counter/stepper motor drive - system calibrations and phase compensation - temperature sensor - voltage sag detect meets accuracy spec for iec, ansi, & jis. low power consumption current input optimized for sense resistor. gnd-referenced signals with single supply on-chip 2.5 v reference (25 ppm/c typ) power supply monitor simple three-wire digital serial interface ?auto-boot? mode from serial e 2 prom. power supply configurations: va+ = +5 v; agnd = 0 v; vd+ = +3.3 v to +5 v description the cs5461a is an integrated power measure- ment device which combines two ? analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip. it is designed to accurately measure instantaneous current and voltage, and calculate v rms , i rms , instanta- neous power, apparent power, and active power for single-phase, 2- or 3-wire power metering applications. the cs5461a is optimized to interface to shunt resistors or current tran sformers for current mea- surement, and to resistive dividers or potential transformers for voltage measurement. the cs5461a features a bi-directional serial in- terface for communication with a processor, and a programmable energy-to-pulse output func- tion. additional featur es include on-chip functionality to facilitate system-level calibration, temperature sensor, voltage sag detection, and phase compensation. ordering in formation: see page 41. va+ vd+ iin+ iin- vin+ vin- vrefin vrefout agnd xin xout cpuclk dgnd cs sdo sdi sclk int voltage reference system clock /k clock generator serial interface e-to-f power monitor pfmon x1 reset digital filter calibration mode power calculation engine 4th order ? modulator 2nd order ? modulator temperature sensor digital filter pga hpf option hpf option e1 e2 e3 x10 aug ?05 ds661f1
cs5461a 2 ds661f1 table of contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. characteristics & s pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 voltage and current measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 power measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 linearity performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 voltage channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 current channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 performing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 energy pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 normal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 alternate pulse forma t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.3 mechanical counter format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.4 stepper motor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.5 pulse output e3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.6 anti-creep for the pulse ou tputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.7 design examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 voltage sag-detect feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 on-chip temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 power-down states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.10 oscillator characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.11 event handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.11.1 typical interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.12 serial port overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.12.1 serial port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.13 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
cs5461a ds661f1 3 6. register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 configuration regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 current and voltage dc offset register ( i dcoff ,v dcoff ) . . . . . . . . . . . . . . 26 6.3 current and voltage gain register ( i gn ,v gn ) . . . . . . . . . . . . . . . . . . . . . . 26 6.4 cycle count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 pulseratee 1,2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 instantaneous current, vo ltage and power registers ( i , v , p ) . . . . . . . . 27 6.7 active (real) power registers ( p active ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.8 i rms and v rms registers ( i rms , v rms ) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.9 power offset register ( p off ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10 status register a nd mask register ( status , mask ) . . . . . . . . . . . . . . . . 28 6.11 current and voltage ac offset register ( v acoff , i acoff ) . . . . . . . . . . . . . 29 6.12 pulseratee 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.13 temperature register ( t ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.14 system gain register ( sys gain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.15 pulsewidth register ( pw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.16 voltage sag duration register ( vsag duration ) . . . . . . . . . . . . . . . . . . . . 30 6.17 voltage sag level register ( vsag level ) . . . . . . . . . . . . . . . . . . . . . . . . 30 6.18 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.19 temperature ga in register ( t gain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.20 temperature offs et register ( t off ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.21 apparent power register ( s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. system calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 channel offset and gain calibr ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.1 calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.1.1 duration of calibration sequence . . . . . . . . . . . . . . . . . . . . . 33 7.1.2 offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.2.1 dc offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . 33 7.1.2.2 ac offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . 34 7.1.3 gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.3.1 ac gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.3.2 dc gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.4 order of calibration seque nces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 active power offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. auto-boot mode using e 2 prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 auto-boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2 auto-boot data for e 2 prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 suggested e 2 prom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. basic application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. environmental, manufacturing, & handling information . . . . . . . . . . . . . . . . . 41 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
cs5461a 4 ds661f1 list of figures figure 1. cs5461a read and write timing diagrams ............................................................... 11 figure 2. data flow............................................................................................................ ......... 13 figure 3. normal format on pulse outputs e1 and e2 ................................................................ 16 figure 4. alternate pulse format on e1 and e2 .......................................................................... 17 figure 5. mechanical counter format on e1 and e2 .................................................................. 17 figure 6. stepper motor format on e1 and e2 ............................................................................ 18 figure 7. voltage sag detect ................................................................................................... ... 19 figure 8. oscillator connection................................................................................................ ... 20 figure 9. calibration data flow ................................................................................................ .. 33 figure 10. system calibration of offset. ..................................................................................... 33 figure 11. system calibration of gain ........................................................................................ 34 figure 12. example of ac gain calibration ................................................................................ 34 figure 13. another example of ac gain calibration .................................................................. 34 figure 14. typical interface of e 2 prom to cs5461a ................................................................ 36 figure 15. typical connection diagram (single-phase, 2-wire ? direct connect to power line) 37 figure 16. typical connection diagram (single-phase, 2-wire ? isolated from power line) ...... 38 figure 17. typical connection diagram (single-phase, 3-wire) .................................................. 38 figure 18. typical connection diagram (single-phase, 3-wire ? no neutral available) ............. 39 list of tables table 1. current channel pga configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2. e1 and e2 pulse output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
cs5461a ds661f1 5 1. overview the cs5461a is a cmos monolithic power measurement device with a computation engine and an en- ergy-to-frequency pulse output. the cs5461a co mbines a programmable-gain amplifier, two ? ana- log-to-digital converters (adcs), system calibr ation and a computation engine on a single chip. the cs5461a is designed for power measurement applic ations and is optimized to interface to a cur- rent-sense resistor or transformer for current meas urement, and to a resistive divider or potential trans- former for voltage measurement. the voltage and cu rrent channels provide programmable gains to accommodate various input levels from a wide vari ety of sensing elements. with single +5 v supply on va+/agnd, both of the cs5461a?s input channels c an accommodate common mode as well as signal levels between (agnd - 0.25 v) and va+. additionally, the cs5461a is equipped with a computation engine that calculates i rms , v rms , apparent power and active (real) power. to facilitate communicat ion to a microprocessor, the cs5461a includes a simple three-wire serial interface which is spi? and microwire? compatible. the cs5461a provides three outputs for energy registration. e1 and e2 are designed to directly drive a mechanical counter or stepper motor, or interface to a microprocessor. the pulse output e3 is designed to assist with meter cal- ibration.
cs5461a 6 ds661f1 2. pin description clock generator crystal out crystal in 1,24 xout, xin - the output and input of an inverting amplif ier. oscillation occurs when connected to a crystal, providing an on-chip system clock. alte rnatively, an external clock can be supplied to the xin pin to provide the system clock for the device. cpu clock output 2 cpuclk - output of on-chip oscillator which can drive one standard cmos load. control pins and serial data i/o serial clock input 5 sclk - a schmitt trigger input pin. clocks data fr om the sdi pin into the receive buffer and out of the transmit buffer onto the sdo pin when cs is low. serial data output 6 sdo -serial port data output pin.sdo is forced into a high impedance state when cs is high. chip select 7 cs - low, activates the serial port interface. mode select 8 mode - high, enables the ?auto-boot? mode. the mode pin is pulled low by an internal resistor. high frequency energy output 18 e3 - active low pulses with an output frequency proportional to the active power. used to assist in system calibration. reset 19 reset - a schmitt trigger input pin. low activates reset, all internal registers (some of which drive output pins) are set to their default states. interrupt 20 int - low, indicates that an enabled event has occurred. energy output 21,22 e1 , e2 - active low pulses with an output frequency pr oportional to the active power. indicates if the measured energy is negative. serial data input 23 sdi - serial port data input pin. data will be input at a rate determined by sclk. analog inputs/outputs differential voltage inputs 9,10 vin+, vin- - differential analog input pins for the voltage channel. differential current inputs 15,16 iin+, iin- - differential analog input pins for the current channel. voltage reference output 11 vrefout - the on-chip voltage reference output. t he voltage reference has a nominal magni- tude of 2.5 v and is referenced to the agnd pin on the converter. voltage reference input 12 vrefin - the input to this pin establishes the voltage reference for the on-chip modulator. power supply connections positive digital supply 3 vd + - the positive digital supply. digital ground 4 dgnd - digital ground. positive analog supply 14 va+ - the positive analog supply. analog ground 13 agnd - analog ground. power fail monitor 1 7 pfmon - the power fail monitor pin monitors the analog supply. if pfmon?s voltage threshold is not met, a low-supply detect (lsd) bit is set in the status register. vrefin 12 voltage reference input vrefout 11 voltage reference output vin- 10 differential voltage input vin+ 9 differential voltage input mode 8 mode select cs 7 chip select sdo 6 serial data ouput sclk 5 serial clock dgnd 4 digital ground vd+ 3 positive digital supply cpuclk 2 cpu clock output xout 1 crystal out agnd 13 analog ground va+ 14 positive analog supply iin- 15 differential current input iin+ 16 differential current input pfmon 17 power fail monitor e3 18 high frequency energy output reset 19 reset int 20 interrupt e1 21 energy output 1 22 sdi 23 serial data input xin 24 crystal in e2 energy output 2
cs5461a ds661f1 7 3. characteristics & specifications recommended operating conditions analog characteristics ? min / max characteristics and specifications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 5 v 5%; agnd = dgnd = 0 v; vrefin = +2.5 v. all voltages with respect to 0 v. ? mclk = 4.096 mhz. parameter symbol min typ max unit positive digital power supply vd+ 3.135 5.0 5.25 v positive analog power supply va+ 4.75 5.0 5.25 v voltage reference vrefin - 2.5 - v specified temperature range t a -40 - +85 c parameter symbol min typ max unit linearity performance active power accuracy all gain ranges (note 1) input range 0.1% - 100% p active -0.1- % current rms accuracy all gain ranges (note 1) input range 1.0% - 100% input range 0.3% - 1.0% input range 0.1% - 0.3% i rms - - - 0.1 0.2 3.0 - - - % % % % voltage rms accuracy all gain ranges (note 1) input range 5% - 100% v rms -0.1- % analog inputs (both channels) common mode rejection (dc, 50, 60 hz) cmrr 80 - - db common mode + signal all gain ranges -0.25 - va+ v analog inputs (current channel) differential input range (gain = 10) [(iin+) - (iin-)] (gain = 50) iin - - 500 100 - - mv p-p mv p-p total harmonic distortion (gain = 50) thd 80 94 - db crosstalk with voltage channel at full scale (50, 60 hz) - -115 - db input capacitance (gain = 10) (gain = 50) ic - - 32 52 - - pf pf effective input impedance eii 30 - - k ? noise (referred to input) (gain = 10) (gain = 50) n i - - - - 22.5 4.5 v rms v rms offset drift (without the high-pass filter) od - 4.0 - v/c gain error (note 2) ge - 0.4 % analog inputs (voltage channel) differential input range {(vin+) - (vin-)} vin - 500 - mv p-p total harmonic distortion thd 65 75 - db crosstalk with current channel at full scale (50, 60 hz) - -70 - db input capacitance all gain ranges ic - 0.2 - pf effective input impedance eii 2 - - m ? noise (referred to input) n v --140v rms offset drift (without the hi gh-pass filter) od - 16.0 - v/c gain error (note 2) ge - 3.0 %
cs5461a 8 ds661f1 analog characteristics (continued) 1. applies when the hpf option is enabled. 2. applies before system calibration. 3. all outputs unloaded. all inputs cmos level. 4. measurement method for psrr: vrefin tied to vref out, va+ = vd+ = 5 v, a 150 mv (zero-to-peak) (60 hz) sinewave is imposed onto the +5 v dc supply voltage at va+ and vd+ pins. the ?+? and ?-? input pins of both input channels are shorted to agnd. then the cs5461a is co mmanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. the (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into th e (zero-to-peak) value of the sinusoidal voltage (measured in mv) that would need to be applied at the channel?s inpu ts, in order to cause the same digital sinusoidal output. this voltage is then defined as veq. psrr is then (in db) : 5. when voltage level on pfmon is sagging, and lsd bit is at 0, the voltage at which lsd bit is set to 1. 6. if the lsd bit has been set to 1 (because pfmon voltage fell below pmlo), this is the voltage level on pfmon at which the lsd bit can be permanently reset back to 0. voltage reference notes: 7. the voltage at vrefout is measured across the tem perature range. from these measurements the following formula is used to calculate the vrefout temperature coefficient:. 8. specified at maximum recommended output of 1 a, source or sink. parameter symbol min typ max unit temperature channel temperature accuracy t - 5 - c power supplies power supply currents (active state) i a+ i d+ (va+ = vd+ = 5 v) i d+ (va+ = 5 v, vd+ = 3.3 v) psca pscd pscd - - - 1.3 2.9 1.7 - - - ma ma ma power consumption active state (va+ = vd+ = 5 v) (note 3) active state (va+ = 5 v, vd+ = 3.3 v) stand-by state sleep state pc - - - - 21 12 8 10 28 16.5 - - mw mw mw w power supply rejection ratio (dc, 50 and 60 hz) (note 4) voltage channel current channel psrr 45 70 65 75 - - db db pfmon low-voltage trigger threshold (note 5) pmlo 2.3 2.45 - v pfmon high-voltage power-on trip point (note 6) pmhi - 2.55 2.7 v parameter symbol min typ max unit reference output output voltage vrefout +2.4 +2.5 +2.6 v temperature coefficient (note 7) tc vref - 25 60 ppm/c load regulation (note 8) ? v r -610mv reference input input voltage range vrefin +2.4 +2.5 +2.6 v input capacitance - 4 - pf input cvf current - 25 - na psrr 20 150 v eq --------- - ?? ?? ?? log ? = (vrefout max - vrefout min ) vrefout avg ( ( 1 t a max - t a min ( ( 1.0 x 10 ( ( 6 tc vref =
cs5461a ds661f1 9 digital characteristics ? min / max characteristics and specifications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 5v 5%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? mclk = 4.096 mhz. notes: 9. all measurements performed under static conditions. 10. if a crystal is used, then xin frequency must remain bet ween 2.5 mhz - 5.0 mhz. if an external oscillator is used, xin frequency range is 2.5 mhz - 20 mhz, but k must be set so that mclk is between 2.5 mhz - 5.0 mhz. 11. if external mclk is used, then the duty cycle must be between 45% and 55% to maintain this specification. 12. the frequency of cpuclk is equal to mclk. 13. the minimum fscr is limited by the maximum allowed gain register value. the maximum fscr is limited by the full-scale signal applied to the channel input. 14. configuration register bits pc[6:0] are set to ?0000000?. 15. the mode pin is pulled low by an internal resistor. parameter symbol min typ max unit master clock characteristics master clock frequency int ernal gate oscillator (note 10) mclk 2.5 4.096 20 mhz master clock duty cycle 40 - 60 % cpuclk duty cycle (note 11 and 12) 40 60 % filter characteristics phase compensation range (voltage channel, 60 hz) -2.8 - +2.8 input sampling rate dclk = mclk/k - dclk/8 - hz digital filter output word ra te (both channels) owr - dclk/1024 - hz high-pass filter corner frequency -3 db - 0.5 - hz full scale calibration range ( referred to input ) (note 13) fscr 25 - 100 %f.s. channel-to-channel time-shift error (note 14) 1.0 s input/output characteristics high-level input voltage all pins except xin and sclk and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage (vd = 5 v) all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.8 1.5 0.2 vd+ v v v low-level input voltage (vd = 3.3 v) all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.48 0.3 0.2 vd+ v v v high-level output voltage i out = +5 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = -5 ma v ol --0.4v input leakage current (note 15) i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf
cs5461a 10 ds661f1 switching characteristics ? min / max characteristics and specifications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = 5 v 5% vd+ = 3.3 v 5% or 5 v 5%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? logic levels: logic 0 = 0 v, logic 1 = vd+. notes: 16. specified using 10% and 90% points on wave-form of interest. output loaded with 50 pf. 17. oscillator start-up time varies with crystal paramete rs. this specification does not apply when using an external clock source. parameter symbol min typ max unit rise times any digital input except sclk (note 16) sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times any digital input except sclk (note 16) sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xt al = 4.096 mhz (note 17) t ost -60-ms serial po rt timing serial clock frequency sclk - - 2 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns sdi timing cs falling to sclk rising t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sdo timing cs falling to sdo driving t 6 -2050ns sclk falling to new data bit (hold time) t 7 -2050ns cs rising to sdo hi-z t 8 -2050ns auto-boot timing serial clock pulse width low pulse width high t 9 t 10 8 8 mclk mclk mode setup time to reset rising t 11 50 ns reset rising to cs falling t 12 48 mclk cs falling to sclk rising t 13 100 8 mclk sclk falling to cs rising t 14 16 mclk cs rising to driving mode low (to end auto-boot sequence). t 15 50 ns sdo guaranteed setup time to sclk rising t 16 100 ns
cs5461a ds661f1 11 t 1 t 2 t 3 t 4 t 5 msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb command time 8 sclks high byte mid byte low byte cs sclk sdi t 10 t 9 reset sdo sclk cs last 8 bits sdi mode stop bit d ata from e e p r o m t 16 t 4 t 5 t 14 t 15 t 7 t 13 t 12 t 11 (input) (input) (o u t p u t ) (o u t p u t ) (o u t p u t ) (input) sdi write timing (not to scale) sdo read timing (not to scale) figure 1. cs5461a read and write timing diagrams auto-boot sequence timing (not to scale) t 1 t 2 msb msb-1 lsb com m and tim e 8 sclks sync0 or sync1 com m and sync0 or sync1 com m and msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb high byte mid byte low byte cs sdo sclk sdi t 6 t 7 t 8 sync0 or sync1 com m and unknow n
cs5461a 12 ds661f1 absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes . notes: 18. va+ and agnd must satisfy {(va+) - (agnd)} + 6.0 v. 19. vd+ and agnd must satisfy {(vd+) - (agnd)} + 6.0 v. 20. applies to all pins including continuous over-voltage conditions at the analog input pins. 21. transient current of up to 100 ma will not cause scr latch-up. 22. maximum dc input current for a power supply pin is 50 ma. 23. total power dissipation, including all input currents and output currents. parameter symbol min typ max unit dc power supplies (notes 18 and 19) positive digital positive analog vd+ va+ -0.3 -0.3 - - +6.0 +6.0 v v input current, any pin except supplies (notes 20, 21, 22) i in --10ma output current, any pin except vrefout i out --100ma power dissipation (note 23) p d --500mw analog input voltage all analog pins v ina - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5461a ds661f1 13 4. theory of operation the cs5461a is a dual-channel analog-to-digital con- verter (adc) followed by a computation engine that per- forms power calculations and energy-to-pulse conversion. the flow diagram for the two data paths is depicted in figure 2 . the analog inputs are structured with two dedicated channels, voltage and current, then optimized to simplify interf acing to sensing elements. the voltage-sensing element introduces a voltage waveform on the voltage channel input vin and is sub- ject to a gain of 10x. a second-order, delta-sigma mod- ulator samples the amplified signal for digitization. simultaneously, the current-sensing element introduces a voltage waveform on the current channel input iin and is subject to the two selectable gains of the pro- grammable gain amplifier (pga). the amplified signal is sampled by a fourth-order, delta-sigma modulator for digitization. both converters sample at a rate of mclk/8, the over-sampling provides a wide dynamic range and simplified an ti-alias filter design. 4.1 digital filters the decimating digital filters on both channels are sinc 3 filters followed by 4th-order, iir filters. the single-bit data is passed to the low-pass decimation filter and out- put at a fixed word rate. the output word is passed to the iir filter to compensate for the magnitude roll-off of the low-pass filtering operation. an optional digital high-pass filter ( hpf in figure 2 ) re- moves any dc component from the selected signal path. by removing the dc component from the voltage and/or the cu rrent channel, any dc content will also be removed from the calculated active power as well. with both hpfs enabled, the dc component will be removed from the calculated v rms and i rms as well as the appar- ent power. 4.2 voltage and current measurements the digital filter output word is then subject to a dc off- set adjustment and a gain calibration (see section 7. system calibration on page 33). the calibrated mea- surement is available to th e user by reading the instan- taneous voltage and current registers. the root mean square (rms) calculations are per- formed on n instantaneous voltage and current sam- ples, v n and i n respectively (where n is the cycle count), using the formula: and likewise for v rms , using v n . i rms and v rms are ac- cessible by register reads, which are updated once ev- ery cycle count (referred to as a computational cycle). 4.3 power measurements the instantaneous voltage and current samples are multiplied to obtain the instantaneous power (see fig- ure 2 ). the product is then averaged over n conver- sions to compute active power and used to drive energy pulse outputs e1 , e2 and e3 . output e3 provides a uni- form pulse stream that is proportional to the active pow- er and is designed for system calibration. to generate a value for the accumulated active energy over the last computation cyc le, the active power can be multiplied by the time duration of the computation cycle. voltage sinc 3 + x v* gn x v * current sinc 3 + x i* gn delay reg delay reg hpf option x i* rms v* rms e1 iir i * i dcoff * v dcoff * pga iir x + + energy-to-pulse x e3 + x + configuration register * digital filter digital filter hpf option x s * 2nd order ? modulator 4th order ? modulator x10 + i acoff * + + v acoff * + e2 n n n n p * active n n p off * p * x x sys gain * pc6 pc5 pc4 pc3 pc2 pc1 pc0 6 pulseratee 1,2 * pulseratee 3 * energy-to-pulse * denotes register name. figure 2. data flow. i rms i n n0 = n1 ? n ------------------- - =
cs5461a 14 ds661f1 the apparent power is the combination of the active power and reactive power, without reference to an im- pedance phase angle, and is calculated by the cs5461a using the following formula: the apparent power is registered once every computa- tion cycle. 4.4 linearity performance the linearity of the v rms , i rms , and active power mea- surements (befor e calibration) will be within 0.1% of reading over the ranges specified, with respect to the in- put voltage levels required to cause full-scale readings in the i rms and v rms registers. refer to linearity per- formance specifications on page 7. until the cs5461a is calibrated, the accuracy of the cs5461a (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed to within 0.1%. see section 7. system calibration on page 33. the accuracy of the internal calculations can often be improved by selecting a value for the cycle count register that will cause the time duration of one computation cycle to be equal to (or very close to) a whole-number of power-line cycles (and n must be greater than or equal to 4000). sv rms i rms =
cs5461a ds661f1 15 5. functional description 5.1 analog inputs the cs5461a is equipped with two fully differential in- put channels. the inputs vin and iin are designated as the voltage and current channel inputs, respectively. the full-scale differential input voltage for the current and voltage channel is 250 mv p . 5.1.1 voltage channel the output of the line-voltag e resistive divider or trans- former is connected to the vin+ and vin- input pins of the cs5461a. the voltage channel is equipped with a 10x, fixed-gain amplifier. the full-scale signal level that can be applied to the voltage channel is 250 mv. if the input signal is a sine wave the maximum rms voltage at a gain 10x is: which is approximately 70.7% of maximum peak volt- age. the voltage channel is also equipped with a volt- age gain register , allowing for an additional programmable gain of up to 4x. 5.1.2 current channel the output of the current-se nse resistor or transformer is connected to the iin+ and iin- input pins of the cs5461a. to accommodate different current-sensing elements, the current channel incorporates a program- mable gain amplifier (pga ) with two programmable in- put gains. configuration register bit igain (see table 1) defines the two gain selections and corresponding max- imum input-signal level. for example, if igain=0, the current channel?s pga gain is set to 10x. if the input signals are pure sinusoids with zero phase shift, the maximum peak differential signal on the current or voltage channel is 250 mv p . the in- put-signal levels are approximately 70.7% of maximum peak voltage producing a full-scale energy pulse regis- tration equal to 50% of absolute maximum energy pulse registration. this will be discussed further in section 5.4 energy pulse output on page 16. the current gain register also allows for an additional programmable gain of up to 4x. if an additional gain is applied to the voltage and/or current channel, the maxi- mum input range should be adjusted accordingly. 5.2 high-pass filters by removing the offset from either channel, no error component will be gen erated at dc when computing the active power. by removing the offset from both chan- nels, no error component will be generated at dc when computing v rms , i rms , and apparent power. configura- tion register bits vhpf and ihpf activate the hpf in the voltage and current channel respectively. 5.3 performing measurements the cs5461a performs me asurements of instanta- neous voltage (v n ) and current (i n ), and calculates in- stantaneous power (p n ) at an output word rate (owr) of where k is the clock divider setting in the configuration register . the rms voltage (v rms ), rms current (i rms ), and ac- tive power (p active ) are computed using n instanta- neous samples of v n , i n and p n respectively, where n is the value in the cycle count register (n) and is referred to as a ?computation cycle? . the apparent power (s) is the product of v rms and i rms . a computation cycle is derived from the master clock (mclk), with frequency: under default conditions & with k = 1, n = 4000, and mclk = 4.096 mhz ? the owr = 4000 hz and the computationcycle= 1hz. all measurements are avail able as a percentage of full scale. the format for signed registers is a two?s comple- ment, normalized value between -1 and +1. the format for unsigned registers is a normalized value between 0 and 1. a register value of represents the maximum possible value. at each instantaneous meas urement, the crdy bit will be set (logic 1) in the status register , and the int pin will become active if the crdy bit is unmasked in the mask register . at the end of each computation cycle, the drdy bit will be set in the status register , and the igain maximum input range 0250mv10x 1 50 mv 50x table 1. current channel pga configuration 250mv p 2 --------------------- 176.78mv rms ? owr mclk k ? () 1024 ----------------------------- = computation cycle owr n --------------- = 2 23 1 ? () 2 23 ----------------------- - 0.99999988 =
cs5461a 16 ds661f1 int pin will become active if the drdy bit is unmasked in the mask register . when these bits are set, they must be cleared (logic 0) by the user before they can be asserted again. if the cycle count register (n) is set to 1, all output cal- culations are instantaneou s, and drdy, like crdy, will indicate when instantaneous measurements are fin- ished. some calculations are inhibited when the cycle count is less than 2. 5.4 energy pulse output the cs5461a provides three output pins for energy reg- istration. the e1 and e2 pins provide a simple interface which energy can be regist ered. these pins are de- signed to directly connect to a stepper motor or electro- mechanical counter. e1 and e2 pins can be set to one of four pulse output formats, normal, alternate, stepper motor, or mechanical counter. table 2 defines the pulse output format, which is controlled by bits alt in the configuration register , and mech and step in the control register. the e3 pin is designated for system calibration, the pulse rate can be selected to reach a frequency of 512 khz. the pulse output frequency of e1 and e2 is directly pro- portional to the active power calculated from the input signals. to calculate the output frequency on e1 and e2 , the following transfer function can be utilized: with mclk = 4.096 mhz, pf = 1, and default settings, the pulses will have an aver age frequency equal to the frequency setting in the pulseratee 1,2 register when the input signals applied to the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. when mclk/k is not equal to 4.096 mhz, the user should scale the pulseratee 1,2 register by a factor of 4.096 mhz/(mclk/k) to get the actual pulse rate out- put. 5.4.1 normal format the normal format is the default. figure 3 illustrates the output format on pins e1 and e2 . the e1 pin outputs ac- tive-low pulses with a frequency proportional to the ac- tive power. the e2 pin is the energy direction indicator. positive energy is represented by a pulse on the e1 pin while the e2 pin remains high. negative energy is rep- resented by synchronous pulses on both the e1 pin and the e2 pin. the pulseratee 1,2 register defines the average fre- quency on output pin e1 , when full-scale input signals are applied to the voltage and current channels. the maximum pulse frequency from the e1 pin alt step mech format 000 normal 0 x 1 mechanical counter 0 1 0 stepper motor 1 x 1 alternate pulse table 2. e1 and e2 pulse output format freq e = average frequency of e1 and e2 pulses [hz] vin = rms voltage across vin+ and vin- [v] vgain = voltage channel gain iin = rms voltage across iin+ and iin- [v] igain = current channel gain pf = power factor pulseratee 1,2 = maximum frequency on e1 and e2 [hz] vrefin = voltage at vrefin pin [v] freq e vin vgain iin igain pf pulseratee 12 , vrefin 2 ------------------------------------------------------------------------------------------------------------------------------- ----------------- = e1 positive energy burst negative energy burst . . . . . . . . . . . . e2 t dur figure 3. normal format on pulse outputs e1 and e2
cs5461a ds661f1 17 is (mclk/k)/16. the pulse duration (t dur ) is an integer multiple of mclk cycles, approximately equal to: the maximum pulse duration (t dur ) is determined by the sampling rate and the minimum is defined by the maxi- mum pulse frequency. the t dur limits are: the pulse width register (pw) does not affect the nor- mal format. 5.4.2 alternate pulse format setting bits mech = 1 and step = 0 in the control register and alt = 1 in the configuration register con- figures the e1 and e2 pins for alternating pulse format output (see figure 4 ). each pin produces alternating ac- tive-low pulses with a pulse duration (t pw ) defined by the pulse width register (pw): if mclk = 4.096 mhz, k = 1, and pw = 1 then t pw = 0.25 ms. to ensure that pulses occur on the e1 and e2 output pins when full-scale input signals are ap- plied to the voltage and current channels, then: the pulse frequency (freq e ) is determined by the pulseratee 1,2 register and can be calculated using the transfer function. the energy direction is not defined in the alternate pulse format. 5.4.3 mechanical counter format setting bits mech = 1 and step = 0 in the control register and bit alt = 0 in the configuration register enables e1 and e2 for mechanical counters and similar discrete counting instruments. when energy is nega- tive, pulses appear on e2 (see figure 5). when energy is positive, the pulses appear on e1 . the pulse width is defined by the pulsewidth register and will limit the out- put pulse frequency (freq e ). by default, pw = 512 samples, if mclk = 4.096 mhz and k = 1 then t pw = 128 ms. to ensure that pulses will occur, the pulseratee 1,2 register must be set to an appropriate value. 5.4.4 stepper motor format setting bits step = 1 and mech = 0 in the control register and bit alt = 0 in the configuration register configures the e1 and e2 pins for stepper motor format. when the accumulated active power equals the defined t dur sec () 1 pulseratee 12 , 8 -------------------------------------------- ? 1 (mclk/k)/16 8 ----------------------------------- t dur sec () 1 (mclk/k)/1024 8 ---------------------------------------- - << figure 4. alternate pulse format on e1 and e2 e1 ... ... e2 ... ... ... t pw freq e t pw ms () pw (mclk/k)/1024 ---------------------------------------- - = pulseratee 12 , 1 t pw ----------- - < t pw e1 positive energy negative energy ... ... ... ... e2 freq e figure 5. mechanical counter format on e1 and e2
cs5461a 18 ds661f1 energy level, the energy output pins (e1 and e2 ) alter- nate changing states (see figure 6). the duration (t edge ) between the alternating states is defined by the transfer function: the direction the motor will ro tate is determined by the order of the state changes. when energy is positive, e1 will lead e2 . when energy is negative, e2 will lead e1 . the pulse width register (pw) does not affect the step- per motor format. 5.4.5 pulse output e3 the pulse output e3 is designed to a ssist with meter cal- ibration. the pulse-output frequency of e3 is directly proportional to the active power calculated from the in- put signals. e3 pulse frequency is derived using a sim- ular transfer function as e1 , but is set by the value in the pulseratee 3 register . the e3 pin outputs negative and positive energy, but has no energy direction indicator. 5.4.6 anti-creep for the pulse outputs anti-creep allows the measurement element to maintain an energy level, such that when the magnitude of the accumulated active power is below this level, no energy pulses are output. anti-creep is enabled by setting bit fac in the control register for e3 and bit eac in the control register for e1 and e2 . for low-frequency pulse output formats (i.e. mechanical counter and stepper motor formats), the active power is accumulated over time. when a designated energy lev- el is reached (determined by the transfer function) a pulse is generated on e1 and/or e2 . if active power with alternating polarity occurs during the accumulation peri- od (e.g. random noise at zero power levels), the accura- cy of the registered energy will be maintained. for high-frequency pulse output formats (i.e. normal and alternate pulse formats), the active power is accu- mulated over time until a 8x buffer is defined. then, when the designated energy level is reached, a pulse is generated on e1 and/or e2 . for pulse outputs with high frequencies and power levels close to zero, the extend- ed buffer prevents random noise from being registered as active energy. 5.4.7 design examples example #1: the maximum rated levels for a power line meter are 250 v rms and 20 a rms. the required number of puls- es per second on e1 is 100 pulses per second (100 hz), when the levels on the power line are 220 v rms and 15 a rms. with a 10x gain on the voltage and current channel the maximum input signal is 250 mv p (see section 5.1 an- alog inputs on page 15). to prevent over-driving the channel inputs, th e maximum rated rm s input levels will register 0.6 in v rms and i rms by design. therefore the voltage level at the chan nel inputs will be 150 mv rms when the maximum rated levels on the power lines are 250 v rms and 20 a rms. solving for pulseratee 1,2 using the transfer function: therefore with pf = 1 and the pulseratee 1,2 register is set to: example #2: the required number of pulses per unit energy present on e1 is specified to be 500 pulses per kwhr, given that the line voltage is 250 vrms and the line current is 20 arms. in such a situation, the stated line voltage and current do not determine the appropriate pulseratee 1,2 setting. to achieve full-scale readings in the instanta- e1 e2 positive energy negative energy ... ... ... ... t edge figure 6. stepper motor format on e1 and e2 t edge sec () 1 freq e --------------------- - = pulseratee 12 , freq e vrefin 2 vin vgain iin pf ------------------------------------------------------------------ - = vin 220v 150mv () 250v () ? () 132mv == iin 15a 150mv () 20a () ? () 112.5mv == pulseratee 100 2.5 2 0.132 10 0.1125 10 ----------------------------------------------------------------- 420.8754hz ==
cs5461a ds661f1 19 neous voltage and current registers, a 250 mv, dc-lev- el signal is applied to the channel inputs. as in example #1, the voltage and current channel gains are 10x, and the voltage leve l at the channel inputs will be 150 mv rms when the levels on the power lines are 250 v rms and 20 a rms. in order to achieve 500 pulse-per-kw hr per unit-energy, the pulseratee 1,2 register setting is determined using the following equation: therefor, the pulseratee 1,2 register is approximately 1.929 hz. the pulseratee 1,2 register cannot be set to a frequency of exactly 1.929 hz. the closest setting is 0x00003e = 1.9375 hz. to improve the accuracy, either gain register can be programmed to correct for the round-off error. this val- ue would be calculated as if (mclk/k) is not equal to 4.096 mhz, the pulseratee 1,2 register must be scaled by a correction factor of: therefore if (mclk/k) = 3.05856 mhz the value of pulseratee 1,2 register is 5.5 voltage sag-detect feature status bit vsag in the status register, indicates a volt- age sag occurred in the power line voltage. for a volt- age sag condition to be identified, the absolute value of the instantaneous voltage must be less than the voltage sag level for more than half of the voltage sag duration (see figure 7 ). to activate voltage sag detect, a voltage sag level must be specified in the voltage sag level register (vsag level ), and a voltage sag duration must be spec- ified in the voltage sag duration register (vsag duration ). the voltage sag level is specified as the average of the absolute instantaneous voltage. voltage sag duration is specified in terms of adc cycles. 5.6 on-chip temperature sensor the on-chip temperature sensor is designed to assist in characterizing the measurement element over a desired temperature range. once a temperature characteriza- tion is performed, the temperature sensor can then be utilized to assist in compen sating for temp erature drift. temperature measurements are performed during con- tinuous conversions and stored in the temperature register . the temperature register (t) default is cel- sius scale ( o c). the temperature gain register (t gain ) and temperature offset register (t off ) are constant val- ues allowing for temperature scale conversions. the temperature update rate is a function of the number of adc samples. with mclk = 4.096 mhz and k = 1 the update rate is: the cycle count register (n) must be set to a value greater than one. status bit tup in the status register, indicates when the temperature register is updated. the temperature offset register sets the zero-degree measurement. to improve temperature measurement accuracy, the zero-degree offset should be adjusted af- ter the cs5461a is initializ ed. temperature offset cali- bration is achieved by adjusting the temperature offset register (t off ) by the differential temperature ( ? t) mea- sured from a calibrated digital thermometer and the cs5461a temperature sensor. a one-degree adjust- ment to the temperature register (t) is achieved by p ulseratee 12 , 500pulses kwhr ----------------------------- - 1hr 3600s ---------------- 1kw 1000w ------------------- 250mv 150mv 250v ------------------- ?? ?? ------------------------- 250mv 150mv 20a ------------------- ?? ?? ------------------------- = vgn or ign pulseratee 1.929 ----------------------------------- 1.00441 ? 0x404830 == 4.096mhz (mclk/k) ---------------------------- pulseratee 12 , pulseratee 12 , 4.096 3.05856 --------------------- 1.929hz 2.583hz ? = level duration figure 7. voltage sag detect 2240 samples (mclk/k)/1024 ---------------------------------------- - 0.56 sec =
cs5461a 20 ds661f1 adding 2.737649x10 -4 to the temperature offset regis- ter (t off ). therefore, if t off = -0.09104831 and ? t = -7.0 ( o c), then or 0xf419bc (2?s compliment notation) is stored in the temperature offset register (t off ). to convert the temperature register (t) from a celsius scale ( o c) to a fahrenheit scale ( o f) utilize the formula applying the above relationship to the cs5461a tem- perature measurement algorithm if t off = -0.09296466 and t gain = 23.799 for a celsius scale, then the modified values are t off = -0.08809772 (0xf4b937) and t gain = 42.8382 (0x55ad29) for a fahrenheit scale. 5.7 voltage reference the cs5461a is specified for operation with a +2.5 v reference between the vrefin and agnd pins. to uti- lize the on-chip 2.5 v reference, connect the vrefout pin to the vrefin pin of the device. the vrefin pin can be used to connect external filtering and/or refer- ences. 5.8 system initialization upon powering up, the digital circuitry is held in reset until the analog voltage reaches 4.0 v. at that time, an eight-xin-clock-period delay is enabled to allow the os- cillator to stabilize. the cs5461a will then initialize. a hardware reset is initiated when the reset pin is as- serted with a minimum pulse width of 50 ns. the reset signal is asynchronous, with a schmitt-trigger input. once the reset pin is de-asserted, an eight-xin-clock-period delay is enabled . a software reset is initiat ed by writing the command of 0x80. after a hardware or software reset, the internal registers (some of which drive output pins) will be reset to their default values. status bit drdy in the status register, indicates the cs5461a is in its active state and ready to receive commands. 5.9 power-down states the cs5461a has two power -down states, stand-by and sleep. in the stand-by st ate all circuitry except the voltage reference and crystal oscillator is turned off. to return the device to the active state a power-up com- mand is sent to the device. in sleep state all circuitry except the instruction decoder is turned off. when the power-up command is sent to the device, a system initialization is performed (see section 5.8 system initialization on page 20). 5.10 oscillator characteristics the xin and xout pins are the input and output of an inverting amplifier configured as an on-chip oscillator, as shown in figure 8. the oscillator circuit is designed to work with a quartz crystal. to reduce circuit cost, two load capacitors c1 and c2 are integrated in the device, from xin to dgnd, and xout to dgnd. pcb trace lengths should be minimize d to reduce stray capaci- tance. to drive the device from an external clock source, xout should be left unconnected while xin is driven by the external circuitr y. there is an amplifier be- tween xin and the digital section which provides cmos-level signals. this am plifier works with sinusoi- dal inputs so there are no problems with slow edge times. the cs5461a can be driven by an external oscillator ranging from 2.5 to 20 mhz, but the k divider value must be set such that the internal mclk will run somewhere between 2.5 mhz and 5 mhz. the k divider value is set with the k[3:0] bits in the configuration register . as an example, if xin = mclk = 15 mhz, and k is set to 5, then dclk is 3 mhz, which is a valid value for dclk. t off t off t ? ( + 2.737649 10 4 ? ) ? = t off 0.09104831 7.0 ? ( + 2.737649 10 4 ? ) ? ? 0.09296466 ? == f o 9 5 -- - c o 17.7778 + () = tf o ?? 9 5 -- - t gain () tc o ?? t off 17.7778 2.737649 10 4 ? ? () + () + [] = oscillator circuit dgnd xin xout c1 c1 = 22 pf c2 c2 = figure 8. oscillator connection
cs5461a ds661f1 21 5.11 event handler the int pin is used to indicate that an internal error or event has taken place in the cs5461a. writing a logic 1 to any bit in the mask register allows the corresponding bit in the status register to activate the int pin. the in- terrupt condition is cleared by writing a logic 1 to the bit that has been set in the status register . the behavior of the int pin is controlled by the imode and iinv bits of the configuration register . if the interrupt ou tput signal format is set for either falling or rising edge, the duration of the int pulse will be at least one dclk cycle (dclk = mclk/k). 5.11.1 typical interrupt handler the steps below show how interrupts can be handled. initialization : 1) all status bits are cl eared by writing 0xffffff to the status register. 2) the condition bits wh ich will be used to generate interrupts are then set to logic 1 in the mask reg- ister. 3) enable interrupts. interrupt handler routine : 4) read the status register. 5) disable all interrupts. 6) branch to the proper interrupt service routine. 7) clear the status register by writing back the read value in step 4. 8) re-enable interrupts. 9) return from interrupt service routine. this handshaking procedure ensures that any new in- terrupts activated between steps 4 and 7 are not lost (cleared) by step 7. 5.12 serial port overview the cs5461a incorporates a serial port transmit and re- ceive buffer with a command decoder that interprets one-byte (8 bits) commands as they are received. there are four types of commands; instructions, synchroniz- ing, register writes and register reads (see section 5.13 commands on page 22). instructions are one byte in length and will interrupt any instruction currently executing. instructions do not affect register reads currently being transmitted. synchronizing commands are one byte in length and only affect the serial in terface. synchronizing com- mands do not affect operations currently in progress. register writes must be followed by three bytes of data. register reads can return up to four bytes of data. commands and data are transf erred most-significant bit (msb) first. figure 1 on page 11, defines the serial port timing and required sequence necessary to write to and read from the serial port receive and transmit buffer, re- spectively. while reading data from the serial port, com- mands and data can be simu ltaneously written. starting a new register read command while data is being read will terminate the curr ent read in progress. this is ac- ceptable if the remainder of the current read data is not needed. during data reads, the serial port requires input data. if a new command and data is not sent, sync0 or sync1 must be sent. 5.12.1 serial port interface the serial port interface is a ?4-wire? synchronous serial communications interface. the interface is enabled to start excepting sclks when cs (chip select) is assert- ed. sclk (serial bit-clock) is a schmitt-trigger input that is used to strobe the data on sdi (serial data in) into the receive buffer and out of the transmit buffer onto sdo (serial data out). if the serial port interface becomes unsynchronized with respect to the sclk input, any attempt to clock valid commands into the serial interface may result in unex- pected operation. the serial port interface must then be re-initialized by one of the following actions: - drive the cs pin high, then low. - hardware reset (drive reset pin low, for at least 10 s). - issue the serial port initialization sequence , which is 3 (or more) sync1 command bytes (0xff) followed by one sync0 command byte (0xfe). if a resynchronization is necessary, it is best to re-initial- ize the part either by hardwar e or software reset (0x80), as the state of the part may be unknown. imode iinv int pin 0 0 active-low level 0 1 active-high level 10 low pulse 11 high pulse table 3. interrupt configuration
cs5461a 22 ds661f1 5.13 commands all commands are 8-bits in length. any byte that is not lis ted in this section is invalid . commands that write to regis- ters must be followed by 3 bytes of data. commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent which can exec ute during the original read). all commands except reg- ister reads, register writes, and sync0 & sync1 will abort any currently executing commands. 5.13.1 start conversions initiates acquiring measurements and calculating results. the device has two modes of acquisition. c3 modes of acquisition/measurement 0 = perform a single computation cycle 1 = perform continuou s computation cycles 5.13.2 sync0 and sync1 the serial port can be in itialized by asserting cs or by sending three or more consecutive sync1 commands fol- lowed by a sync0 command. the sync0 or sync1 can also be sent while sending data out. sync 0 = last byte of a serial port re-initialization sequence. 1 = used during reads and serial port initialization. 5.13.3 power-up/halt if the device is powered-down, power- up/halt will initiate a power on reset. if the part is already powered-on, all computations will be halted. 5.13.4 power-down and software reset to conserve power the cs5461a has two power-down states. in stand-by state all circuitry, except the analog/digital clock generators, is turned off. in the sleep state all circui try, except the instruction decoder, is turned off. bringing the cs5461a out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabiliz e the analog oscillator. s[1:0] power-down state 00 = software reset 01 = halt and enter stand-by power saving state. this state allows quick power-on 10 = halt and enter sleep power saving state. 11 = reserved b7 b6 b5 b4 b3 b2 b1 b0 1110c3000 b7 b6 b5 b4 b3 b2 b1 b0 1111111sync b7 b6 b5 b4 b3 b2 b1 b0 10100000 b7 b6 b5 b4 b3 b2 b1 b0 100s1s0000
cs5461a ds661f1 23 5.13.5 register read/write the read/write informs the command decoder that a register access is required. during a read operation, the ad- dressed register is loaded into an output buffer and cl ocked out by sclk. during a wr ite operation, the data is clocked into an input buffer and transferred to the addressed register upon completion of the 24 th sclk. w/r write/read control 0 = read 1 = write ra[4:0] register address bits (bits 5 through 1) of the read/write command. address ra[4:0] name description 0 00000 config configuration 1 00001 i dcoff current dc offset 2 00010 i gn current gain 3 00011 v dcoff voltage dc offset 4 00100 v gn voltage gain 5 00101 cycle count number of a/d conversions used in one computation cycle (n)). 6 00110 pulseratee 1,2 sets the e1 and e2 energy-to-frequency output pulse rate. 7 00111 i instantaneous current 8 01000 v instantaneous voltage 9 01001 p instantaneous power 10 01010 p active active (real) power 11 01011 i rms rms current 12 01100 v rms rms voltage 14 01110 p off power offset 15 01111 status status 16 10000 i acoff current ac (rms) offset 17 10001 v acoff voltage ac (rms) offset 18 10010 pulseratee 3 sets the e3 energy-to-frequency output pulse rate. 19 10011 t temperature 20 10100 sys gain system gain 21 10101 pw pulse width register for mechanical counter output mode 23 10111 vsag duration voltage sag duration 24 11000 vsag level voltage sag level threshold 26 11010 mask interrupt mask 28 11100 ctrl control 29 11101 t gain temperature sensor gain 30 11110 t off temperature sensor offset 31 11111 s apparent power note: for proper operation, do not attempt to write to unspecified registers. b7 b6 b5 b4 b3 b2 b1 b0 0w/r ra4 ra3 ra2 ra1 ra0 0
cs5461a 24 ds661f1 5.13.6 calibration the cs5461a can perform system calibrations. proper inpu t signals must be applied to the current and voltage channel before performing a designated calibration. cal[4:0]* designates calibration to be performed 01001 = current channel dc offset 01010 = current channel dc gain 01101 = current channel ac offset 01110 = current channel ac gain 10001 = voltage channel dc offset 10010 = voltage channel dc gain 10101 = voltage channel ac offset 10110 = voltage channel ac gain 11001 = current and voltage channel dc offset 11010 = current and voltage channel dc gain 11101 = current and voltage channel ac offset 11110 = current and voltage channel ac gain *values for cal[4:0] not spec ified should not be used. b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 cal4 cal3 cal2 cal1 cal0
cs5461a ds661f1 25 6. register description 1. ?default? => bit status after power-on or reset 2. any bit not labeled is reserved. a zero should always be used when writing to one of these bits. 6.1 configuration register address: 0 default = 0x000001 pc[6:0] phase compensation. a 2?s complement number which sets a delay in the voltage channel rel- ative to the current channel. when mclk = 4.096 mhz and k = 1, the phase adjustment range is approximately 2.8 degrees with each step approximat ely 0.04 degrees (assuming a power line frequency of 60 hz). if (mclk/k) is not 4.096 mhz, the values for the range and step size should be scaled by the factor 4.096 mhz / (mc lk/k). default setting is 0000000 = 0.0215 de- gree phase delay at 60 hz (when mclk = 4.096 mhz). igain sets the gain of the current pga. 0 = gain is 10x (default) 1 = gain is 50x ewa allows the e1 and e2 pins to be configured as open-collector output pins. 0 = normal outputs (default) 1 = only the pull-down device of the e1 and e2 pins are active imode, iinv interrupt configuration bi ts. select the desired pin behavior for indication of an interrupt. 00 = active-low level (default) 01 = active-high level 10 = high-to-low pulse 11 = low-to-high pulse epp allows the e1 and e2 pins to be controlled by the eop and edp bits. 0 = normal operation of the e1 and e2 pins. (default) 1 = eop and edp bits defines the e1 and e2 pins. eop eop defines the value of the e1 pin when epp = 1. 0 = logic level low (default) edp edp defines the value of the e2 pin when epp = 1. 0 = logic level low (default) alt alternate pulse format, e1 and e2 becomes active low alternating pulses with an output fre- quency proportional to the active power. 0 = normal (default), mechanical counter or stepper motor format 1 = alternate pulse format, also mech = 1 vhpf (ihpf) enables the high-pass filt er on the voltage (current) channel. 0 = high-pass filter disabled (default) 1 = high-pass filter enabled 23 22 21 20 19 18 17 16 pc6 pc5 pc4 pc3 pc2 pc1 pc0 igain 15 14 13 12 11 10 9 8 ewa imode iinv epp eop edp 76543210 alt vhpf ihpf icpu k3 k2 k1 k0
cs5461a 26 ds661f1 icpu inverts the cpuclk clock. in order to reduce the level of noise present when analog signals are sampled, the logic driven by cpuclk should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when cpuclk is driving rising-edge logic k[3:0] clock divider. a 4-bit binary number used to divi de the value of mclk to generate the internal clock dclk. the internal clock frequency is dclk = mclk/k. the value of k can range be- tween 1 and 16. a value of ?0000? will se t k to 16 (not zero). k = 1 at reset. 6.2 current and voltage dc offset register ( i dcoff ,v dcoff ) address: 1 (current dc offs et); 3 (voltage dc offset) default = 0x000000 the dc offset registers (i dcoff ,v dcoff ) are initialized to 0.0 on reset. when dc offset ca libration is performed, the register is updated wit h the dc offset measured over a computation cycle. drdy will be asserted at the end of the calibration. this register may be read and stored fo r future system offset compensation. the value is repre- sented in two's complement notation and in the range of -1.0 i dcoff , v dcoff < 1.0, with the binary point to the right of the msb. 6.3 current and voltage gain register ( i gn ,v gn ) address: 2 (current gain); 4 (voltage gain) default = 0x400000 = 1.000 the gain registers (i gn ,v gn ) are initialized to 1.0 on reset. when either a ac or dc gain calibration is performed, the register is updated with the ga in measured over a comp utation cycle. drdy will be asserted at the end of the calibration. this register may be read and stored for future system gai n compensation. the value is in the range 0.0 i gn ,v gn < 3.9999, with the binary point to the right of the second msb. 6.4 cycle count register address: 5 default = 0x000fa0 = 4000 cycle count, denoted as n, determines the length of one computation cycle . during continuous conversions, the computation cycle frequency is (mclk/k)/(1024 ? n). a one second computational cycle period occurs when mclk = 4.096 mhz, k = 1, and n = 4000. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0
cs5461a ds661f1 27 6.5 pulseratee 1,2 register address: 6 default = 0xfa000 = 32000.00 hz pulseratee 1,2 sets the frequency of the e1 and/or e2 pulses. the smallest valid frequency is 2 -4 with 2 -5 incre- mental steps. a pulse rate higher than (mclk/k)/8 will result in a puls e rate setting of (m clk/k)/8. the value is represented in unsigned notation, with the binary point to the right of bit 5. 6.6 instantaneous current, voltage and power registers ( i , v , p ) address: 7 (instantaneous current); 8 (insta ntaneous voltage); 9 (instantaneous power) i and v contain the instantaneous meas ured values for current and voltage, respectively. the instantaneous voltage and current samples ar e multiplied to obtain instan taneous power (p). the value is represented in two's complement notation and in the range of -1.0 i, v, p < 1.0, with the binary point to the right of the msb. 6.7 active (real) power registers ( p active ) address: 10 the instantaneous power is averaged over each comput ation cycle (n conversions) to compute active power (p active ). the value is represented in two's complement notation and in the range of -1.0 p active < 1.0, with the binary point to the right of the msb. 6.8 i rms and v rms registers ( i rms , v rms ) address: 11 (i rms ); 12 (v rms ) i rms and v rms contain the root mean square (rms) value of i and v, calculated over each computation cycle. the value is represented in unsigned bi nary notation and in the range of 0.0 i rms ,v rms < 1.0, with the binary point to the left of the msb. 6.9 power offset register ( p off ) address: 14 default = 0x000000 power offset (p off ) is added to the instantaneous power being accumulated in the p active register and can be used to offset contributions to the en ergy result that are caused by undesi rable sources of energy that are in- herent in the system. the value is represented in two's complement notation and in the range of -1.0 p off < 1.0, with the binary point to the right of the msb. msb lsb 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5461a 28 ds661f1 6.10 status register and mask register ( status , mask ) address: 15 ( status ) ; 26 (mask) default = 0x000001 (status register), 0x000000 (mask register) the status register indicates status within the chip. in normal operation, wr iting a '1' to a bit will cause the bit to reset. writing a '0 ' to a bit will not change it?s current state. the mask register is used to control the activation of the int pin. placing a logic '1' in a mask bit will allow the corresponding bit in the status register to activate the int pin when the status bit is asserted. drdy data ready. during conversions, this bit will i ndicate the end of computation cycles. for cali- brations, this bit indicates the end of a calibration sequence. crdy conversion ready. indicates a ne w conversion is ready. this will occur at the output word rate. ior current out of range. set when the instantaneous current register overflows. vor voltage out of range. set when the instantaneous voltage register overflows. iror i rms out of range. set when the i rms register overflows. vror v rms out of range. set when the v rms register overflows. eor energy out of range. set when p active overflows. tup temperature updated. indicates the temperature register has updated. tod modulator oscillation detected on the temperat ure channel. set when t he modulator oscillates due to an input above full scale. vod (iod) modulator oscillation det ected on the voltage (c urrent) channel. set wh en the modulator oscil- lates due to an input above full scale. the level at which th e modulator oscillate s is significantly higher than the voltage (current) channel?s differential input voltage range. note: the iod and vod bits may be ?falsely? triggered by very brief voltage spikes from the power line. this event should not be confused with a dc overload situation at the in- puts, when the iod and vod bits will re-asse rt themselves even after being cleared, multiple times. lsd low supply detect. set when the voltage at th e pfmon pin falls below the low-voltage thresh- old (pmlo), with respect to agnd pin. the lsd bit cannot be reset until the voltage at pfmon pin rises back above the high-voltage threshold (pmhi). vsag indicates a voltag e sag has occurred. see section 5.5 voltage sag-detect feature on page 19. ic invalid command. normally logic 1. set to logic 0 if an invalid comman d is received or the sta- tus register has not been successfully read. 23 22 21 20 19 18 17 16 drdy crdy ior vor 15 14 13 12 11 10 9 8 iror vror eor 76543210 tup tod vod iod lsd vsag ic
cs5461a ds661f1 29 6.11 current and voltage ac offset register ( v acoff , i acoff ) address: 16 (current ac offset ); 17 (voltage ac offset) default = 0x000000 the ac offset registers (v acoff , i acoff ) are initialized to zero on reset, allowing for uncalibrated normal operation. ac offset calibration updates these registers. this s equence lasts approximately (6n + 30) adc cycles (where n is the value of the cycle count register ). drdy will be asserted at the e nd of the calibration. these values may be read and stored for future s ystem ac offset compensation. the value is represented in two's comple- ment notation and in the range of -1.0 v acoff , i acoff < 1.0, with the binary point to the right of the msb. 6.12 pulseratee 3 register address: 18 default = 0xfa0000 = 32000.00 hz pulseratee 3 sets the freq uency of the e3 pulses. the register?s smallest valid frequency is 2 -4 with 2 -5 incre- mental steps. a pulse rate higher than (mclk/k)/8 will result in a puls e rate setting of (m clk/k)/8. the value is represented in unsigned notation, with th e binary point to the right of bit #5. 6.13 temperature register ( t ) address: 19 t contains measurements from the on-chip temperature sensor. measurements are performed during continu- ous conversions, with the default the celsius scale ( o c). the value is represented in two's complement notation and in the range of -128.0 t < 128.0, with the binary point to the right of the eighth msb. 6.14 system gain register ( sys gain ) address: 20 default = 0x500000 = 1.25 system gain (sys gain ) determines the one?s density of the cha nnel measurements. small changes in the mod- ulator due to temperature can be fine adjusted by changi ng the system gain. the value is represented in two's complement notation and in the range of -2.0 < sys gain < 2.0, with the binary point to the right of the second msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb -(2 1 )2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22
cs5461a 30 ds661f1 6.15 pulsewidth register ( pw ) address: 21 default = 0x000200 = 512 sample periods pw sets the pulsewidth of e1 and e2 pulses in alternate pulse and mechanical counter format. the width is a function of number of sample periods. the default corresponds to a pulsewidth of 512 samples/[(mclk/k)/1024] = 128 msec with mclk = 4.096 mhz and k = 1. the value is represented in un- signed notation. 6.16 voltage sag duration register ( vsag duration ) address: 23 default = 0x000000 voltage sag duration (vsag duration ) defines the number of instantaneous voltage m easurements utilized to de- termine a voltage level sag event (vsag level ). setting this register to zero will disable voltage sag-detect. the value is represented in unsigned notation. 6.17 voltage sag level register ( vsag level ) address: 24 default = 0x000000 voltage sag level (vsag level ) defines the voltage level that the magnit ude of input samples, averaged over the sag duration, must fall below in order to register a sag condition. this value is represented in unsigned notation and in the range of 0 vsag level < 1.0, with the binary point to the right of the msb. msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5461a ds661f1 31 6.18 control register register address: 28 default = 0x000000 fac determines if anti-creep is enabled for pulse output e3 . 0 = disable anti-creep (default) 1 = enabled anti-creep eac determines if anti-creep is enabled for pulse output e1 and/or e2 . 0 = disable anti-creep (default) 1 = enabled anti-creep stop terminates the auto-boot sequence. 0 = normal (default) 1 = stop sequence mech mechanical counter format, e1 or e2 becomes active low pulses with an output frequency pro- portional to the active power 0 = normal (default) or stepper motor format 1 = mechanical counter format, also alt = 0 intod converts int output pin to an open drain output. 0 = normal (default) 1 = open drain nocpu saves power by disabling the cpuclk pin. 0 = normal (default) 1 = disables cpuclk noosc saves power by disab ling the crystal oscillator. 0 = normal (default) 1 = oscillator circuit disabled step stepper motor format, e1 and e2 becomes active low pulses wi th an output frequency propor- tional to the active power 0 = normal format (default) 1 = stepper motor format, also mech = 0 and alt = 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 fac eac stop 76543210 mech intod nocpu noosc step
cs5461a 32 ds661f1 6.19 temperature gain register ( t gain ) address: 29 default = 0x34e2e7 = 26.443169 sets the temperature channel gain. temperature gain (t gain ) is utilized to convert fr om one temperature scale to another. the celsius scale ( o c) is the default. values are represent ed in unsigned notation and in the range of 0 t gain < 128, with the binary point to the right of the seventh msb. 6.20 temperature offset register ( t off ) address: 30 default = 0xf3e7d0 = -0.094488 temperature offset (t off ) is used to remove the temperature channel?s offset at the zero degree reading. values are represented in two's complement notation and in the range of -1.0 t off < 1.0, with the binary point to the right of the msb. 6.21 apparent power register ( s ) address: 31 apparent power (s) is the product of the v rms and i rms . the value is represented in unsigned binary notation and in the range of 0.0 s < 1.0, with the binary point to the left of the msb. msb lsb 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 ..... 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24
cs5461a ds661f1 33 7. system calibration 7.1 channel offset and gain calibration the cs5461a provides digital dc offset and gain com- pensation that can be applied to the instantaneous volt- age and current measurements, and ac offset compensation to the voltage and current rms calcula- tions. since the voltage and current channels have indepen- dent offset and gain regist ers, system offset and/or gain can be performed on either channel without the calibration results from one channel affecting the oth- er. the computational flow of th e calibration sequences are illustrated in figure 9 . the flow applies to both the volt- age channel and current channel. 7.1.1 calibration sequence the cs5461a must be operating in its active state and ready to accept valid commands. refer to section 5.13 commands on page 22. the calibration algorithms are dependent on the value n in the cycle count register (see figure 9 ). upon completion, the results of the cali- bration are available in their corresponding register. the drdy bit in the status register will be set. if the drdy bit is to be output on the int pin, then drdy bit in the mask register must be set. the initial values stored in the ac gain and offset regist ers do affect the calibration results. 7.1.1.1 duration of calibration sequence the value of the cycle count register (n) determines the number of conversions performed by the cs5461a during a given calibration sequence. for dc offset and gain calibrations, the calibration sequence takes at least n + 30 conversion cycles to complete. for ac offset calibrations, the sequence takes at least 6n + 30 adc cycles to complete, (about 6 computation cycles). as n is increased, the accuracy of calibration results will in- crease. 7.1.2 offset ca libration sequence for dc- and ac offset calibrations, the vin pins of the voltage and iin pins of the current channels should be connected to their ground-reference level. see figure 10 . the ac offset registers must be set to the default (0x000000). 7.1.2.1 dc offset calibration sequence channel gain should be set to 1.0 when performing dc offset calibration. initiate a dc offset calibration. the dc offset registers are updated with the negative of the av- erage of the instantaneous samples taken over a com- putational cycle. upon completion of the dc offset calibration the dc offset is stored in the corresponding dc offset register. the dc offset value will be added to each instantaneous measurement to cancel out the dc figure 9. calibration data flow in modulator + x to v*, i* registers filter n v rms *, i rms * registers dc offset* gain* 0.6 + + + * denotes readable/writable register n + x n inverse x -1 rms ac offset* n x -1 + + - xgain + - external connections 0v + - ain+ ain- cm + - figure 10. system calibration of offset.
cs5461a 34 ds661f1 component present in the system during conversion commands. 7.1.2.2 ac offset calibration sequence corresponding offset registers i acoff and/or v acoff should be cleared prior to in itiating ac offset calibra- tions. initiate an ac offset calibration. the ac offset reg- isters are updated with an offset value that reflects the rms output level. upon completion of the ac offset cal- ibration the ac offset is stored in the corresponding ac offset register. the ac offset register value is subtract- ed from each successive v rms and i rms calculation. 7.1.3 gain calibration sequence when performing gain calibrations, a reference signal should be applied to the vin pins of the voltage and iin pins of the current channe ls that represents the de- sired maximum signal level. figure 11 shows the basic setup for gain calibration. for gain calibrations, there is an absolute limit on the rms voltage levels that are selected for the gain-cali- bration input signals. the maximum value that the gain registers can attain is 4. ther efore, if the signal level of the applied input is low enough that it causes the cs5461a to attempt to set either gain register higher than 4, the gain ca libration result will be invalid and all cs5461a results obtained while performing measure- ments will be invalid. if the channel gain registers are initially set to a gain oth- er then 1.0, ac gain calibration should be used. 7.1.3.1 ac gain calibration sequence the corresponding gain register should be set to 1.0, unless a different init ial gain value is desired. initiate an ac gain calibration. the ac gain calibration algorithm computes the rms value of the reference signal applied to the channel inputs. the rms register value is then di- vided into 0.6 and the quotient is stored in the corre- sponding gain register. each instantaneous measurement will be multipli ed by its corresponding ac gain value. a typical rms calibration va lue which allows for reason- able over-range margin would be 0.6 or 60% of the volt- age and current channel?s maximum input voltage level. two examples of ac gain calibration and the updated digital output codes of the channel?s instantaneous data registers are shown in figures 12 and 13. figure 13 shows that a positive (or negative), dc-level signal can be used even though an ac gain calibration is being ex- + - + - external connections in+ in- cm + - + - xgain reference signal figure 11. system calibration of gain v rms register = 230 / 2 x 1 / 250 0.65054 250 mv 230 mv 0 v -230 mv -250 mv 0.9999... 0.92 -0.92 -1.0000... v rms register = 0.600000 250 mv 230 mv 0 v -230 mv -250 mv 0.84853 -0.84853 before ac gain calibration (vgn register = 1) after ac gain calibration (vgn register changed to approx. 0.9223) instantaneous voltage register values instantaneous voltage register values sinewave sinewave 0.92231 -0.92231 input signal input signal figure 12. example of ac gain calibration v rms register = 230 = 0.92 250 mv 230 mv 0 v -250 mv 0.9999... 0.92 -1.0000... v rms register = 0.600000 250 mv 230 mv 0 v -250 mv 0.6000 before ac gain calibration (vgain register = 1) after ac gain calibration (vgai n register changed to approx. 0.65217) instantaneous voltage register values instantaneous voltage register values dc signal dc signal 0.65217 -0.65217 input signal input signal 250 figure 13. another example of ac gain calibration
cs5461a ds661f1 35 ecuted. however, an ac signal should not be used for dc gain calibration. 7.1.3.2 dc gain calibration sequence initiate a dc gain calibration. the corresponding gain register is restored to default (1.0). the dc gain calibra- tion algorithm averages the channel?s instantaneous measurements over one co mputation cycle (n sam- ples). the average is then divided into 1.0 and the quo- tient is stored in the corresponding gain register after the dc gain calibration, the instantaneous register will read at full-scale whenever the dc level of the input signal is equal to the level of the dc calibration signal applied to the inputs during the dc gain calibration.the hpf option should not be enabled if dc gain calibration is utilized. 7.1.4 order of ca libration sequences 1. if the hpf option is enabled, then any dc compo- nent that may be present in the selected signal path will be removed and a dc offs et calibration is not re- quired. however, if the hpf option is disabled the dc offset calibration sequence should be per- formed. when using high-pass filters, it is recommended that the dc offset regi ster for the corresponding channel be set to zero. when performing dc offset calibration, the corresponding gain channel should be set to one. 2. if an ac offset exist, in the v rms or i rms calculation, then the ac offset calibration sequence should be performed. 3. perform the gain calibration sequence. 4. finally, if an ac offset calibration was performed (step 2), then the ac offset may need to be adjusted to compensate for the change in gain (step 3). this can be accomplished by restoring zero to the ac offset register and then perform an ac offset cali- bration sequence. the ad justment could also be done by multiplying the ac offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the ac offset register with the product. 7.2 phase compensation the cs5461a is equipped with phase compensation to cancel out phase shifts introduced by the measurement element. phase compensation is set by bits pc[6:0] in the configuration register . the default value of pc[6:0] is zero. with mclk = 4.096 mhz and k = 1, the phase compensa- tion has a range of 2.8 degrees when the input signals are 60 hz. under these conditions, each step of the phase compensation register (value of one lsb) is ap- proximately 0.04 degrees. for values of mclk other than 4.096 mhz, the range and step size should be scaled by 4.096 mhz/(mclk/k). for power-line fre- quencies other than 60hz, the values of the range and step size of the pc[6:0] bits can be determined by con- verting the above values from angular measurement into time-domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency. 7.3 active power offset the power offset register can be used to offset system power sources that may be resident in the system, but do not originate from the power-line signal. these sources of extra energy in the system contribute unde- sirable and false offsets to the power and energy mea- surement results. after deter mining the amount of stray power, the power offset register can be set to cancel the effects of this unwanted energy.
cs5461a 36 ds661f1 8. auto-boot mode using e 2 prom when the cs5461a mode pin is asserted (logic 1), the cs5461a auto-boot mode is enabled. in auto-boot mode, the cs5461a downloads the required com- mands and register data from an external serial e 2 prom, allowing the cs5461a to begin performing energy measurements. 8.1 auto-boot configuration a typical auto-boot serial connection between the cs5461a and a e 2 prom is illustrated in figure 14 . in auto-boot mode, the cs5461a?s cs and sclk are con- figured as outputs. the cs5461a asserts cs , provides a clock on sclk, and sends a read command to the e 2 prom on sdo. the cs5461 a reads the user-speci- fied commands and register data presented on the sdi pin. the e 2 prom?s programm ed data is utilized by the cs5461a to change the designated registers? default values and begin registering energy. figure 14 also shows the external connections that would be made to a calibrator device, such as a pc or custom calibration board. when the metering system is installed, the calibrator woul d be used to control calibra- tion and/or to program user-specified commands and calibration values into the e 2 prom. the user-specified commands/data will determine the cs5461a?s exact operation, when the auto-boot initialization sequence is running. any of the valid commands can be used. 8.2 auto-boot data for e 2 prom below is an example code set for an auto-boot se- quence. this code is written into the e 2 prom by the us- er. the serial data for such a sequence is shown below in single-byte, hexidecimal notation: - 40 00 00 61 write configuration register , turn high-pass filters on, set k=1. - 44 7f c4 a9 write value of 0x7fc4 a9 to current gain register. - 48 ff b2 53 write value of 0xffb253 to voltage gain register. - 4c 00 7d 00 set pulseratee 1,2 register to 1000 hz. - 74 00 00 04 unmask bit #2 (lsd) in the mask register). - e8 start continuous conversions - 78 00 01 00 write stop bit to control register, to terminate auto-boot initialization sequence. 8.3 suggested e 2 prom devices several industry-standard, serial e 2 proms that will successfully run auto-boot with the cs5461a are listed below: ? atmel at25010, at25020 or at25040 ? national semiconductor nm25c040m8 or nm25020m8 ? xicor x25040si these types of serial e 2 proms expect a specific 8-bit command (00000011) in order to perform a memory read. the cs5461a has been hardware programmed to transmit this 8-bit command to the e 2 prom at the be- ginning of the auto-boot sequence. figure 14. typical interface of e 2 prom to cs5461a cs5461a eeprom eout1 eout2 mode sclk sdi sdo cs sck so si cs connector to calibrator vd+ 5 k 5 k mech. counter stepper motor or
cs5461a ds661f1 37 9. basic application circuits figure 15 shows the cs5461a configured to measure power in a single-phase, 2-wire system while operating in a single-supply configuratio n. in this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. in this type of shunt resistor configuration, the common-mode level of the cs5461a must be referenced to the line side of the power line. this means that the common-mode poten- tial of the cs5461a will trac k the high-voltage levels, as well as low-voltage levels, with respect to earth ground potential. isolation circuitry is required when an earth- ground-referenced communicati on interface is connect- ed. figure 16 shows the same single-phase, two-wire sys- tem with complete isolation from the power lines. this isolation is achieved using three transformers: a general purpose transformer to supply the on-board dc power; a high-precision, low-impedance voltage transformer with very little roll-off/phas e-delay, to measure voltage; and a current transformer to sense the line current. figure 17 shows a single-phase, 3-wire system. in many 3-wire residential power systems within the unit- ed states, only the two line terminals are available (neu- tral is not available). figure 18 shows the cs5461a configured to meter a three-wire system with no neutral available. va+ vd+ cs5461a 0.1 f 470 f 500 ? 470 nf 500 n r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source serial data interface reset 17 2 1 24 19 cs 7 sdi 23 sdo 6 sclk 5 int 20 e1 0.1 f vrefin 12 vrefout 11 agnd dgnd 13 4 3 4.096 mhz 0.1 f 10 k ? 5k ? l r shunt r v- r i- r i+ isolation 120 vac mech. counter stepper motor or 22 21 c i- c i+ c idiff c v- c v+ c vdiff e2 note: indicates common (floating) return. figure 15. typical connection diagram (single-phase, 2-wire ? direct connect to power line)
cs5461a 38 ds661f1 va+ vd+ cs5461a 0.1 f 470 f 500 ? 470 nf 500 ? n r 3 r 4 r burden 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sd sdo sclk int 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 4.095 mhz 0.1 f l 1 l 2 10 k ? 5k ? r 1 r 2 r i+ r i- 22 21 mech. counter stepper motor or 1k ? 1k ? 120 vac 120 vac 240 vac serial data interface 19 7 23 6 5 20 i earth ground c idiff c idiff e1 agnd e2 figure 17. typical connection diagram (single-phase, 3-wire) mech. counter stepper motor or va+ vd+ cs5461a 0.1 f 200 f 200 n 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int 22 e1 21 0.1 f vrefin 12 vrefout 11 agnd dgnd 13 4 3 4.096 mhz 0.1 f 10 k ? 5k ? l m:1 r n:1 low phase-shift potential transformer current transformer r v+ r v- c vdiff r i- r i+ c burden idiff voltage transformer 120 vac 12 vac 12 vac ? 200 ? serial data interface 19 7 23 6 5 20 1k ? 1k ? 1k ? 1k ? e2 figure 16. typical connection diagram (single-phase, 2-wire ? isolated from power line)
cs5461a ds661f1 39 va+ vd+ 0.1 f 470 f 1 k ? 235 nf 500 ? r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 4.096 mhz 0.1 f l 1 l 2 10 k ? 5k ? r i+ r i- r v- serial data interface 19 7 23 6 5 20 isolation 22 21 mech. counter stepper motor or r burden 1k ? 1k ? 240 vac cs5461a note: indicates common (floating) return. c vdiff c i+ c v+ c idiff e1 agnd e2 figure 18. typical connection diagram (single-phase, 3-wire ? no neutral available)
cs5461a 40 ds661f1 10.package dimensions notes: 3. ?d? and ?e1? are reference datums and do not included mo ld flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 4. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 5. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters. e n 12 3 e b 2 a1 a2 a d se ati ng plane e1 1 l side view end v iew top view 24l ssop package drawing
cs5461a ds661f1 41 11. ordering information 12. environmental, manufac turing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 13. revision history model temperature package CS5461A-IS -40 to +85 c 24-pin ssop CS5461A-ISz (lead free) model number peak reflow temp msl rating* max floor life CS5461A-IS 240 c 2 365 days CS5461A-ISz (lead free) 260 c 3 7 days revision date changes a1 dec 2004 advance release pp1 feb 2005 initial pr eliminary release f1 aug 2005 final version updated with most-rec ent characterization data. msl data added. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical a pplications?). cirrus products are not d esigned, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other crit ical applications. inclusio n of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer u ses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corporation.

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